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cml microcircuits communication semiconductor s cmx991/cmx992 rf quadrature transmitter and rf quadrature/low if receiver ? 2011 cml microsystems plc d/991_992/16 june 2011 provisional issue this document describes two separate, high performance, rf ics covering the range: 100mhz 1 to 1ghz. the cmx991 is an rf quadrature transceiver and the cmx992 is an rf quadrature receiver. features applications ? rx (cmx991 and cmx992) o rf mixer with output select o 1st if input select o selectable low if outputs (450khz/455khz) o 1st if variable gain amplifier (vga) o 1st if signal level indicator (sli) o two-mode demodulator o i/q zero-if with differential outputs ? tx (cmx991 only) o i/q modulator to if o image-reject up-converter o if and rf outputs ? if (cmx991 and cmx992) o if lo synthesiser o if vco negative resistance amplifier ? 3.3v low power operation ? analogue/digital multimode radio ? software defined radio (sdr) ? portable, mobile and base station terminals ? data telemetry modems ? tetra (cmx992) ? etsi: en 300 113, en 301 166, en 302 561, en 300 220, ts 102 361 (dmr) ? automatic identification system (ais) transponders ? constant envelope and linear modulation ? compatible with cmx998 (cmx992 only) ? narrowband: e.g. 25khz, 12.5khz, 6.25khz ? wideband: up to 2mhz ? apco project 25 (p25) phase 1 and phase 2 tdma: tia-102.caab ? satellite communications 1 brief description the cmx991 is a single-chip, high performance, rf tran sceiver that provides t he core functions required to implement a full-featured radio transmitter and rece iver. it operates from 100mhz to 1ghz and its i/q architecture supports multiple modulation types and bandwidths with a single radio design. the half- duplex cmx991 integrates tx modulat ors, rx demodulators, if pll and if vco subsystems to minimise the external circuits needed when implementing a co mplete transceiver. user-selected modes suit different application requirements. the tx path includes an i/q modulator to accurately generate modulation at the if frequency, which may then be translated to the final rf frequency by an in tegrated image-reject up-converter system. the i/q modulator if output is also made available for conversion to rf via external circuits, if desired. the rx path includes an integrated 1 st rx mixer having two outputs to support two external 1 st if filter choices, then an integrated 2:1 input mux follo wed by vga and wideband signal level measurement functions, to support agc implementation. the 1 st if signal is then either i/q demodulated to zero-if or mixed to a low if output. the cmx991 provides differential and single-ended rx output options and differential amplifiers for flexible signal conditioning. the cmx992 is a single-chip, high performance, rf re ceiver that includes the core rf and if receive functions of the cmx991 above and can be used in a wide range of narrowband and wideband wireless products, including multi-mode analogue/digital terminals. the cmx992 can be used where highly linear modulations are being used, e.g. for applications such as tetra, where a typical transmitter solution woul d include the cmx998 cartesian feedback transmitter. both devices operate from a single 3.3v supply ov er a temperature range of -40c to +85c and are available in 48-pin vqfn (q3) packages. 1 the cmx991/cmx992 may be used at lower frequencies by usi ng appropriate external components. use below 100mhz is covered in a separate application note available from the cml website.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 2 d/991_992/16 control registers /4 external resonator & varactors power supply integer-n pll c-bus div rx level differential amplifiers t/r if filters 2 x if (e.g 455khz) outputs or i/q outputs lo input power amplifier div lo input tx i/q input (vc)tcxo lna cmx991 if output figure 1 cmx991 ? rf quadrature transceiver control registers /4 external resonator & varactors power supply integer-n pll c-bus div sli differential amplifiers t/r from transmitter if filters 2 x if (e.g 455khz) outputs or i/q outputs lo input cmx992 figure 2 cmx992 ? rf quadrature/low if receiver
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 3 d/991_992/16 contents section page 1 brief descr iption........................................................................................................ 1 1.1 history............................................................................................................. 6 2 block di agrams.......................................................................................................... 7 3 pin list ....................................................................................................................... .8 3.1 signal defi nitions ............................................................................................ 9 4 external co mponents ............................................................................................. 10 4.1 power supply decoup ling ............................................................................ 10 4.2 receiver (cmx 991 and cm x992)................................................................ 11 4.3 transmitter (c mx991 only) .......................................................................... 15 4.4 main local oscilla tor .................................................................................... 16 4.5 if local oscillato r (cmx991 and cmx992) ................................................. 17 5 general d escription ................................................................................................ 19 5.1 overvi ew....................................................................................................... 19 5.2 receiver........................................................................................................ 19 5.3 transmitter (c mx991 only) .......................................................................... 21 5.4 local osc illators ........................................................................................... 22 5.5 v bias .............................................................................................................. 24 5.6 data inte rface ............................................................................................... 24 6 c-bus interface and re gister d escription ........................................................... 25 6.1 general reset comm and (cmx991/ cmx992) ............................................ 27 6.2 general control register (cmx 991/cmx 992) ............................................. 27 6.3 rx control regist er (cmx991/ cmx992)...................................................... 28 6.4 rx mode register (cmx991/ cmx992) ........................................................ 29 6.5 tx control regist er (cmx 991 only) ............................................................. 30 6.6 tx mode register (cmx991 only) ................................................................ 31 6.7 tx gain register (cmx 991 only) ................................................................. 31 6.8 if pll m divider (cmx991/ cmx992) .......................................................... 32 6.9 pll n divider (cmx991/cm x992)............................................................... 33 7 applicati on notes .................................................................................................... 34 7.1 gener al ......................................................................................................... 34 7.2 using the cmx992 wi th the cmx998........................................................... 34 7.3 receiver ga in issues ................................................................................... 34 7.4 oscillator components for alter native intermedi ate frequenc ies................ 35 7.5 rf mixer input matching .............................................................................. 36 7.6 rf mixer if ou tput ma tching ....................................................................... 36 7.7 if input matching .......................................................................................... 37 7.8 signal level indi cator (s li) .......................................................................... 39 7.9 receiver spurious re jection perf ormance .................................................. 41 7.10 receiver i/q filters ....................................................................................... 42 7.11 modulation accura cy .................................................................................... 42 7.12 post i/q modul ator f ilter............................................................................... 44 8 performance sp ecificat ion ..................................................................................... 47 8.1 electrical pe rform ance ................................................................................. 47 8.2 packagi ng ..................................................................................................... 56
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 4 d/991_992/16 table page table 1 pin lis t .............................................................................................................. .... 9 table 2 definition of powe r supply and refe rence vo ltages ............................................ 9 table 3 decoup ling com ponents..................................................................................... 10 table 4 typical rx 1 st mixer input matching components for 455m hz........................... 11 table 5 1 st if filtering co mponents fo r 45m hz ............................................................... 13 table 6 rx i/q differential to single ended amp lifier co mponents ................................ 13 table 7 rx low if (455khz) component s....................................................................... 14 table 8 transmitter com ponents .................................................................................... 15 table 9 i/q modulator ou tput matchi ng com ponents ..................................................... 16 table 10 rx lo input co mponents ................................................................................. 16 table 11 if vco lo internal vco amplif ier tank circuit fo r 180mhz operation .......... 17 table 12 if lo 3 rd order loop filter circui t for 180mhz operation................................ 18 table 13 typical receiv er gain pa rtiti oning.................................................................... 34 table 14 typical if vco circuit values for a variety of if fr equencies......................... 35 table 15 receiver input match circ uit for other oper ating fr equencies ....................... 36 table 16 mixout e quivalent impedanc es...................................................................... 37 table 17 noise figure and gain of if amp, vga, i/q mixer and baseband filters........ 38 table 18 ifip1 port impedance (para llel equivalent circuit models).............................. 38 table 19 if noise figure measurements at 45 mhz ....................................................... 39 table 20 symbol/error table for the tx with 9.6kbps gmsk from an ev9100............... 44 figure page figure 1 cmx991 ? rf quadrature tr ansceiv er ............................................................... 2 figure 2 cmx992 ? rf quadr ature/low if rece iver........................................................ 2 figure 3 cmx991 block di agram ...................................................................................... 7 figure 4 cmx992 block di agram ...................................................................................... 7 figure 5 recommended power suppl y connections and decoup ling............................ 10 figure 6 example external components ? receive 1 st mixer input ................................ 11 figure 7 example external components ? receive 1 st if section.................................. 12 figure 8 example external co mponents ? receiv e i/q output ...................................... 13 figure 9 example external com ponents ? receive low if output ................................ 14 figure 10 example external components ? transmitter................................................. 15 figure 11 example external co mponents ? i/q modul ator output ................................. 16 figure 12 example external components ? rx lo input................................................ 16 figure 13 example external components ? if lo vco external tank circuit .............. 17 figure 14 example external components ? if lo loop f ilter ........................................ 18 figure 15 dc offset calibrati on mode............................................................................. 20 figure 16 cmx991 transmitter arch itectu re ................................................................... 21 figure 17 cmx991/cmx992 if local o scillator.............................................................. 22 figure 18 typical lo input impedanc e............................................................................ 23 figure 19 c-bu s transac tions ........................................................................................ 26 figure 20 receiver gain c ontrol ..................................................................................... 35 figure 21 receiver matching co mponents ..................................................................... 36 figure 22 mixout1 port impedance ( unmatc hed) ......................................................... 37 figure 23 ifip1 input im pedance at 0db attenuation ...................................................... 38
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 5 d/991_992/16 figure 24 typical sli perfor mance ................................................................................. 40 figure 25 typical sli performance in an application circuit ( ev9920b)........................ 40 figure 26 if output response with and without blocki ng signal present ...................... 41 figure 27 typical receiv er i/q frequency res ponse ..................................................... 42 figure 28 tx output with 9.6kbps gmsk fr om an ev9100 ............................................. 43 figure 29 transmitter path if filters ............................................................................... 45 figure 30 transmitter if output showing filter responses wi th ifh bit = ?1?................. 45 figure 31 effect of ifh on 45mhz and 60mhz transmitte r if filters ............................. 46 figure 32 c- bus timing .................................................................................................. 55 figure 33 q3 mec hanical ou tline: ................................................................................... 56
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 6 d/991_992/16 1.1 history version changes date 16 ? clarification of gain and noise of if stage in ?straight in? case (section 7.7) ? editorial changes for consist ency of table header format ? update of receiver gain partition (section 7.3.1) jun 2011 15 ? details of receiver gain switching added (section 7.3.2) ? pll frequency formula added (section 5.4.1) ? phase noise formula typo corrected (m not n) (section 8.1.3.2 note 94) mar 2011 14 ? cmx991: transmitter lo leakage specification clarified and limits adjusted ? cmx991: transmitter lo image typical value updated dec 2010 13 ? transmitter i and q channels shown in error causing a spectrum inversion in tx path. pins txqn and txqp swapped ( table 1) ? editorial error in table 13 corrected. sep 2010 12 ? rx imd minimum specification improved after evaluation of production test fixture (section 8.1.3.2) jun 2010 11 ? redundant series capacitor deleted and s eparate capacitors shown for c3 in figure 7 and table 5 ? extra information on mixer output impedance added (section 7.6). ? table 13 updated. ? extra information added on if gain measurement conditions in (section 7.7). ? extra information added on rx i/q filter, (section 7.10). ? extra information added on tx filter, (section 7.12). ? maximum limits added for ?total current consumption? figures?, (section 8.1.3.1) ? lo leakage performance specification updat ed; clarification of note 7 and 7a; new note 7b; reference corrected in note 11; test frequency of 45mhz moved from note 17 to note 10; gain of i/q filter moved to overall if amplifier and i/q demodulator table (section 8.1.3.2). mar 2010 10 ? pll phase noise specification corrected and definition added ? i/q bandwidth clarified in section 4.2.3.2. jan 2010 9 ? vco specification corrected. it should be 400mhz (max). ? dbv/v terminology clarified. it should be db(v/v) ? clarification of rx 1st mixer input 3rd order intercept point measurement ? correction to c5 in figure 7, the circuit referenced in iip3 measurement nov 2009 8 ? updated with further application information (e.g. if vco options). july 2009 7 ? updated with enhanced application information. may 2009 6 ? original published document for bot h the cmx991 and cmx992 devices. mar 2009 it is always recommended that you check for the late st product datasheet version from the cml website: [ www.cmlmicro.com ].
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 7 d/991_992/16 2 block diagrams limiting vco amp control registers divide by 4 sin cos iampo external resonator & varactors power supply mixinn mixinp ifp1 qampn mixlop txifout qampp rxqn rxqp qampo iampn ifp2 mixout1 mixout2 integer-n pll divide by 2 or 4 c - b u s agnd vbias vccsynth dgnd dvdd txlon fref divide by 4, 2 or 1 vddio txoutp sli sli select / bypass select mixlon vcop vcon doif txip txin txqp txqn rxin rxip lnaon lna control txlop ifinn rdata sclk cdata csn resetn vccif vccrf divide by 2 or 4 txoutn enable iampp figure 3 cmx991 block diagram limiting vco amp control registers divide by 4 sin cos iampo external resonator & varactors power supply mixinn mixinp ifp1 qampn mixlop qampp rxqn rxqp qampo iampp iampn ifp2 mixout1 mixout2 integer-n pll c-bus agnd vbias vccsynth dgnd dvdd fref divide by 4, 2 or 1 vddio sli sli select / bypass mixlon vcop vcon doif rxin rxip lnaon lna control ifinn rdata sclk cdata csn resetn vccrf vccif enable figure 4 cmx992 block diagram
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 8 d/991_992/16 3 pin list package q3 pin no. pin name (cmx991) pin name (cmx992) signal type description 1 vccif vccif power supply for if circuits o/p cmx991: tx se ction positive output 2 txoutp nc nc cmx992: do not connect to this pin, reserved for future use o/p cmx991: tx se ction positive output 3 txoutn nc nc cmx992: do not connect to this pin, reserved for future use 4 nc nc nc do not connect to this pin, reserved for future use 5 nc nc nc do not connect to this pin, reserved for future use i/p cmx991: tx local oscillator negative input 6 txlon nc nc cmx992: do not connect to this pin, reserved for future use i/p cmx991: tx local oscillator positive input 7 txlop nc nc cmx992: do not connect to this pin, reserved for future use 8 mixinn mixinn i/p rx mixer negative input 9 mixinp mixinp i/p rx mixer positive input 10 mixlon mixlon i/p rx mixer local oscillator negative input 11 mixlop mixlop i/p rx mixer local oscillator positive input 12 vccrf vccrf power supply for rf circuits 13 mixout1 mixout1 o/p rx mixer output 1 14 mixout2 mixout2 o/p rx mixer output 2 15 ifip1 ifip1 i/p rx if positive input 1 16 ifip2 ifip2 i/p rx if positive input 2 17 ifinn ifinn i/p rx if negative input 18 sli sli o/p receiver signal level indicator (sli) output 19 rxqn rxqn o/p rxq negative output 20 rxqp rxqp o/p rx q positive output 21 qampp qampp i/p rxq amplifier positive input 22 qampn qampn i/p rxq amplifier negative input 23 qampo qampo o/p low if output or rxq amp output 24 rxin rxin o/p rxi negative output 25 rxip rxip o/p rxi positive output 26 iampp iampp i/p rxi amplifier positive input 27 iampn iampn i/p rxi amplifier negative input 28 iampo iampo o/p rxi amplifier output 29 dgnd dgnd power digital ground 30 csn csn i/p c-bus chip select (active low), used to enable a c-bus data read or write operation on the chip 31 rdata rdata t/s c-bus serial data 3-state output (reply data) to host 32 sclk sclk i/p c-bus clock input from the host 33 cdata cdata i/p c-bus serial data input (command data) from the host 34 resetn resetn i/p c-bus reset (low for reset condition)
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 9 d/991_992/16 package q3 pin no. pin name (cmx991) pin name (cmx992) signal type description 35 dvdd dvdd power supply to digital circuits 36 vddio vddio power supply to c-bus circuits 37 lnaon lnaon o/p control line to enable/disable rx lna 38 vccsynth vccsynth power supply to if integer n pll 39 fref fref i/p reference frequency input 40 doif doif o/p if pll charge pump output 41 vcop vcop i/p if pll vco positive input 42 vcon vcon i/p if pll vco negative input 43 vbias vbias o/p bandgap generated bias voltage ? measurement output i/p cmx991: txq positive input 44 txqp (note 2) nc nc cmx992: do not connect to this pin, reserved for future use i/p cmx991: txq negative input 45 txqn (note 2) nc nc cmx992: do not connect to this pin, reserved for future use i/p cmx991: txi negative input 46 txin nc nc cmx992: do not connect to this pin, reserved for future use i/p cmx991: txi positive input 47 txip nc nc cmx992: do not connect to this pin, reserved for future use o/p cmx991: tx if output 48 txifout nc nc cmx992: do not connect to this pin, reserved for future use e xposed m etal p ad agnd agnd power the exposed metal pad must be electrically connected to analogue ground total = 49 pins (48 pins and central, exposed metal ground pad) table 1 pin list notes: 1) i/p = input o/p = output t/s = 3-state nc = not connected 2) in versions of the datasheet before d/991_992/13 t hese pins were incorrectly referenced as pin 44 = txqn and pin 45 = txqp causing a spec trum inversion at the modulator output. 3.1 signal definitions signal name pins usage av dd vccif, vccrf, vccsynth power supply for analogue circuits. dv dd dvdd power supply for digital circuits. v dd io vddio power supply voltage for digital interface (c-bus). v bias vbias bandgap generated bias voltage used as a reference for differential amplifier stages. decoupling is optional but, if used, a capacitor of >200nf should be connected between v bias and av ss . dv ss dgnd ground for digital circuits. av ss agnd ground for analogue circuits. table 2 definition of power supply and reference voltages
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 10 d/991_992/16 4 external components 4.1 power supply decoupling the cmx991/cmx992 has separate supply pins for t he analogue and digital circuitry: a 3.3v nominal supply is recommended for all circuits but a different voltage for v dd io may be used (see section 5.6). r5 r4 av dd r3 r2 r1 c5 c4 c3 c2 c1 gnd plane for: gnd gnd for: dgnd dvdd vddio vccrf vccif vccsynth agnd dv dd figure 5 recommended power supply connections and decoupling c1 10nf r1 3.3 ? c2 10nf r2 3.3 ? c3 10nf r3 3.3 ? c4 10nf r4 10 ? c5 10nf r5 10 ? table 3 decoupling components notes: 1. maximum tolerances: resistors 5%, capacitors 20% unless otherwise stated 2. it is expected that any low frequency interference on the 3.3 volt supply will be removed by active regulation; a large capacitor is an alternative but may require more board space and so may not be preferred. it is particularly important to ens ure that there is no interference from the v dd io (which supplies the digital i/o) or from any other circuit that may use the dv dd supply (such as a microprocessor), to sensitive analogue supplies (av dd ). it is therefore advisable to use separate power supplies for the digital and analogue circuitry. 3. the supply decoupling shown is intended for rf noise suppression. it is necessary to have a small series impedance prior to the decoupling capacit or for the decoupling to work well; this may be cost effectively done with the re sistor and capacitor values shown. the use of resistors results in small dc voltage drops (up to approx 0.1v). choosing resistor values approximately inversely proportional to the dc current requirements of each supply ensures the dc voltage drop on each supply are reasonably matched. in any case, the dc voltage change that results is well within the design tolerance of the device. if higher im pedance resistors are used (not recommended) then greater care will be needed to ensure the supply vo ltages are maintained within tolerance, even when parts of the device are enabled or disabled. 4. it is advisable to have separate ground planes for the analogue and digital circuits.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 11 d/991_992/16 4.2 receiver (cmx991 and cmx992) the receiver relies on an external lna, filtering and a transmit/receive switch; details can be found in section 5.2. 4.2.1 rx 1 st mixer the rx 1 st mixer has a differential input with a nominal impedance of 300 and series capacitance of 8pf. to ensure optimum performance a balun is required when driving from typical single-ended (un-balanced) lnas or filters. the balun may be a transformer type or implemented using lc networks. a typical matching circuit to the rx 1 st mixer is shown in figure 6. in a particular impl ementation the shunt resistors r1 and r2 may be replaced by a single component ac ross the balun t1 output. the blocking capacitors c3 and c4 may be omitted if the input signals are 0v dc biased. dc should not be applied to the input pins, otherwise damage to the inter nal protection diodes may result. l1 r1 l2 r2 c4 t1 mixinp mixinn input c3 cmx991 cmx992 figure 6 example external components ? receive 1 st mixer input l1 27nh l2 33nh c3 1nf t1 tc1-1-13m+ c4 1nf r1 and r2 nf table 4 typical rx 1 st mixer input matching components for 455mhz
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 12 d/991_992/16 4.2.2 rx 1 st if filtering the output of the cmx991/cmx992 first receive mixer can be switched between mixout1 and mixout2 to support two different external 1 st if filters for different receiver operating modes. the if output should be in the range 10mhz to 150mhz. the integrat ed if amplifier that follows external 1 st if filters has two switchable inputs. it is recommended that an if filt er (e.g. crystal or saw type) be placed between the mixer output and if amplifier input stages to prot ect the if amplifier and subsequent stages from off- channel signals. matching arrangements will vary with the particular filter used, however an example of a typical configuration for a 45mhz if is given in figure 7. the configuration shown only utilises one possible combination of the two 1 st mixer outputs and two if amplifier inputs; the other input and output (ifip2 and mixout2 respectively) could be configured to use a saw filter or operate with a different if frequency or bandwidth, for example. the mixerout1 and mixerout2 pins should have a dc blocking capacitor, as should the if amplifier inputs ifip1 and if ip2. ifinn should be ac coupled to the if filter ground. for additional information see sections 5.2.2 and 7.6. mixout1 mixout2 mixinn mixinp ifip1 ifip2 ifinn cmx991 cmx992 f1 l1 c1 c3a c2 c4 r1 l2 c5 c7 r2 c8 c3b figure 7 example external components ? receive 1 st if section
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 13 d/991_992/16 c1 1nf c7 1nf c2 15pf c8 18pf c3a 3.9pf l1 1h c3b 4.7pf l2 1h c4 4.7pf r1 1200 ? c5 1nf r2 220 ? f1 45g15b1 table 5 1 st if filtering components for 45mhz 4.2.3 rx output 4.2.3.1 i/q output amplifiers the cmx991/cmx992 includes uncommitted differential amplifiers, which may be used to convert the differential i and q output signals to a single ended output. a typical configuration of the amplifier on the q channel (the i channel is identical) is shown in figure 8. this circuit has a linear gain of 1.5 and is not optimum for rejection of common m ode signals, however in practice per formance is generally satisfactory. users should note that the gain and bandwidth of th is stage can be adjusted by altering the component values and should be configured to suite a particular application. qamp qampo pin 23 rxqn pin19 r1 r2 c1 r3 c2 rxqp pin 20 qampp pin 21 qampn pin 22 figure 8 example external components ? receive i/q output c1 nf r1 10k ? c2 nf r2 10k ? r3 10k ? table 6 rx i/q differential to single ended amplifier components
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 14 d/991_992/16 4.2.3.2 low if output the i/q demodulator output bandwidth has a minimu m of 1mhz, typically 1.4mhz (see section 8.1.3.2), so the output of each i and q demodulator mixer can be configured to mix down to a low 2 nd if and use a demodulator output amplifier to provide gain. a typi cal configuration for the q channel is shown in figure 9. qamp qampo pin 23 25k ceramic filter vbias r2 r3 c2 r4 c3 r1 c1 f1 rxqp pin 20 qampp pin 21 qampn pin 22 figure 9 example external components ? receive low if output c1 100nf r1 1.5k ? c2 47nf r2 1.5k ? c3 33pf r3 1.5k ? f1 cfwl455kefa-b0 r4 4.7k ? table 7 rx low if (455khz) components the components above specify, as an example, a particular ceramic filter (f1) that would typically be used in a 25khz channel application in a system wi th an if frequency of 455khz. the other component values specified (e.g. r1, r3) are determined by the i nput/output impedance of the f ilter used. the filter and other components can be easily changed to allow for other bandwidths or any 2 nd if output up to 1mhz. a different external 2 nd if filter, of different bandwidth, could similarly be connected to the i channel output to support a second modulation bandwidth mode, e.g. to receive a 6.25khz channel signal. the channel to be used is selectable via the general control register ($11), section 6.2, the unused channel being powered-down.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 15 d/991_992/16 4.3 transmitter (cmx991 only) 4.3.1 transmitter details of the transmitter are contained in the transmitter description, section 5.3. the components used around the cmx991 will depend on application requirements, however a typical configuration is shown in figure 10. cmx991 txoutp txoutn av dd vccrf vccrf tx output t1 c1 r1 figure 10 example external components ? transmitter c1 10nf (note 1) t1 4:1 balun with centre tap (note 2) r1 3.3 ? table 8 transmitter components notes: 1 value of c1 is dependant on frequency of operation. at hi gher frequencies an additional low value decoupling capacitor in parallel (e.g. 33pf) may be required for opt imum performance. c1 shoul d be located as close to the centre tap of t1 as possible. 2 example component for t1 is mini-circuits tc4-14+. 3 additional components may be required at thet1 output for optimum match to 50 ? . 4.3.2 if i/q modulator output the i/q modulator can be used on its own, without the up-conversion mixers, by switching the i/q modulator output to the output pin, txifout (pin 48) ? see section 6.5. a typical configuration for this output is shown in figure 11.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 16 d/991_992/16 + 90 i inputs q inputs if lo txif filter cmx991 c1 i/q modulator output txifout txip txin txqn txqp figure 11 example external components ? i/q modulator output c1 1nf table 9 i/q modulator output matching components 4.4 main local oscillator 4.4.1 receiver lo input (cmx991 and cmx992) the main local oscillator input is differential, but the normal configuration will be single ended, with the other input ac coupled to ground as shown in figure 12. to prevent signals present on the local ground affecting the lo, the ground associated with capacitor c2 should be the same ground that is used for the lo source. in this way any ground noise will be co mmon mode at the inputs a and b and will be rejected. lo input divider cmx991 cmx992 c1 c2 a b a = mixlop b = mixlon figure 12 example external components ? rx lo input c1 1nf c2 1nf table 10 rx lo input components the blocking capacitors c1 and c2 may be omitted (i.e point b connected to ground) if the input signals are 0v dc biased. dc should not be applied to the input pins, otherwise damage to the internal protection diodes may result.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 17 d/991_992/16 4.4.2 transmitter lo input (cmx991 only) exactly the same configuration can be used for t he cmx991 tx lo input as for the receiver ( figure 12, table 10). for the transmitter, ?a? in the diagram is pin txlop and ?b? is pin txlon. 4.5 if local oscillator (cmx991 and cmx992) a typical configuration for using the internal vco negative resistance amplifier at 180mhz is shown in figure 13. the other external components required to complete the pll are the loop filter components, see figure 14 ? which shows a 3 rd order loop filter; typical values for a 1khz bandwidth are given in table 12. cmx991 cmx992 l1 cv1 c3 c2 c1 r1 vco negative resistance (nr) amplifier cv2 r2 vcop vcon l1 should have a q>30 input from loop filter vco output buffer amplifier enable enable figure 13 example external components ? if lo vco external tank circuit l1 33nh (note 1) cv1 jdv2s08s c1 6.8 pf (note 2) cv2 jdv2s08s c2 27 pf r1 10k ? c3 27 pf r2 10k ? note 1: tolerance of 2% or better recommended note 2: tolerance of 5% or better recommended table 11 if vco lo internal vco amplifier tank circuit for 180mhz operation
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 18 d/991_992/16 c3 c2 c1 r1 r2 doif (pin 40) output to tank cct figure 14 example external components ? if lo loop filter c1 22nf r1 430 ? c2 470nf r2 12k ? c3 1nf table 12 if lo 3 rd order loop filter circuit for 180mhz operation to inject an external if lo signal, the negative resi stance amplifier should be disabled, with the vcon input decoupled to ground with a 1nf capacitor. the signal is then applied to vcop via a dc blocking capacitor (e.g. 1nf). other circui try shown above, such as the tank circuit, should be not fitted.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 19 d/991_992/16 5 general description 5.1 overview the cmx991/cmx992 are rf quadrature transceiver and receiver ics respectively. each incorporates a superheterodyne receiver section along with if local oscillator circuits. the cmx991 has an i/q modulator with image-rejecting up-converter. t he cmx991/cmx992 i/q architecture supports a wide range of modulation types and various selectable func tions maintain the performance across multiple modulations and bandwidths. the dem odulator outputs are analogue signals with a quadrature (i/q) zero- if signal format that simplifies connection to exter nal adcs. the receiver analogue signal interface also supports a low if output mode. the transmitter interface is analogue i/q format. control of the cmx991/cmx992 is via the serial c-bus (see section 6). 5.2 receiver the cmx991/cmx992 has a flexible multi-standard receiver designed to support multiple digital and analogue radio systems of both const ant envelope and linear modulation ty pes. it is expected that the applied input signal will have been amplified by an exter nal low noise amplifier (lna). the user must determine the need for, and design of, any external im age reject filtering. the cmx991/cmx992 design is optimised for an lna gain of about 13db 2 . it is assumed there is some insertion loss prior to the lna but an overall noise figure of 4db and gain of 8db (approx .) should be provided by the circuits preceding the cmx991/cmx992. a digital control signal is availabl e from the chip, which can be used to enable/disable the lna. use of this signal is recommended as it simplif ies i/q calibration of dc-offsets. a differential input signal to the first mixer on the chip is recommended. the receiver architecture is a superheterodyne type with a 1 st if allowed in the range 10mhz to 150mhz, some typical 1 st ifs being 10.7mhz, 21.4mhz, 45mhz, 70mhz and 150mhz. the cmx991/cmx992 provides a 1 st down converter mixer with excellent linearity and noise figure. the design is intended to meet the challenging requirements of typical pmr/lmr radio systems. 5.2.1 rx 1 st mixer and if filtering the rx 1 st mixer has a differential input with a nominal impedance of 300 ? and nominal input frequency range of 100mhz to 1ghz. the 1 st mixer has selectable lo input dividers: these are /1, /2 and /4 to allow common lo structures with the various tx arch itectures, including use of the cmx998 with the transmitter. the mixer rf lo input is differential but the normal configuration is single ended with the other input ac coupled to ground (see section 4.4.1). the mixer has two selectable outputs to allow the connection of two different 1 st if filters, crystal or saw type, that may be separately enabled under host cont rol. the type of filter used is dependant on the application. the filter should pr ovide rejection of blocking and in termodulation test tones for the subsequent if stages. this 1 st if filter may also provide some useful adjacent channel filtering, but it is likely that the majority of the adjacent c hannel rejection will come in subsequent stages. 5.2.2 if variable gain amplifier (vga) and i/q down-converter mixer there are two selectable inputs to the if amplifier, which is low noise and controlled through the c-bus serial interface (see section 6). the inputs are differential with a common inverting input (pin ifinn) which should be decoupled locally to the ground plane used for the external if elements. the if inputs are high impedance (see section 8.1.3.2) and this allows straightforward matching to if filter components. 2 the precise gain will depend on application and is often a trade-off between intermodulation performance and receiver noise figur e. see also section 7.3.1.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 20 d/991_992/16 a typical configuration is shown in section 4.2.2, figure 7 where the resistor r1 is used to define the resistive load for the filter . the suggested value of 1200 ? can be varied depending on requirements, noting the trade-off between voltage gain and q of the matching arrangements. the input impedance varies slightly with vga setting but the effect of this is minimised by use of the terminating resistor r1. the variable gain may be adjusted by a host proce ssor based on the measured signal level indicator (sli) value or on other criteria such as i/q vect or magnitude. the sli output is an analogue output which is single ended and referenced to ground. following the if amplifier there is a pair of mixers that perform the final down-conversion either to an i/q or low if output. the i/q demodulator has an output bandwidth of 1mhz which allows a low if output of up to 1m hz; typical values may be 450khz, 455khz or 465khz. 5.2.3 i/q filters the i/q outputs include two filters that provide continuous time rejection to serve as anti-alias filters for external adcs. the default filter will give an i/q bandwidth of 1mhz. a narrower filter of 100khz bandwidth is selectable to improve analogue reje ction for narrow-band systems and guarantees image rejection for typical (e.g. sigma-delta) adc solutions. div mixout 1 mixout 2 switch cmx991 cmx992 mixinn mixinp rx mode register ($13,b4) ?cal en? = ?1?. acquire i/q offset circuitry disabled during acquire i/q dc offset figure 15 dc offset calibration mode 5.2.4 dc offset correction the cmx991/cmx992 does not provide direct compensation of dc offs ets in the i/q outputs from the receiver, however it does provide a mode that allows the i/q signals to be measured externally to support easy compensation. to allow optimum measurement of dc offsets it is desirable to remove the input signal to allow fast averaging of the output i.e. without the need to consider the possibility of modulation being present. in this mode the areas of the cmx991/cm x992 that can generate dc offsets remain enabled. the cmx991/cmx992 ?cal en? mode (rx mode register $13, b4, see section 6.4.1) disables the early stages of the receiver, as shown in figure 15.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 21 d/991_992/16 5.3 transmitter (cmx991 only) the transmitter requires analogue i and q (baseband) signal inputs. this i/q input is up-converted by quadrature modulator(s) to a suitable if (txif). this is the modulated signal with the desired modulation, but at an if of typically 45mhz or 90mhz, i.e. typically lower than the final desired (rf) transmit frequency. the txif signal is available at the txifout pin or can be up (or down)converted to final frequency using the cmx991 image reject up-mixer. the txif signal can be optimised by selecting the correct setting of the ifh bit (register $11, b5 see section 6.2.1) for ifs above or below 75mhz. the if lo input applied to the if i/q modulator(s) is generally developed internally (see section 5.4). the lo is divided by either 2 or 4 to generate the quar ature signals used in the modulator. the main lo, used in image-reject up-converter, is generated off-chip. 5.3.1 image-reject up-converter the cmx991 transmitter architecture is shown in figure 16. the image rejection process involves generating txif signals with a quadrature phase relati onship. the txif signals pass through filters to remove harmonic content ? this substantially reduc es the spurious content of the final output. the bandwidth of the filters is selectable as 45m hz, 60mhz, 90mhz or 120mhz (see also section 7.12). the signals are then used in a modulator stage which conver ts to the final frequency. the process results in image cancellation of the unwanted mixing sideband wi th default operation being high side mixing as follows: f rf = f lo - f txif (wanted) f image = f lo + f txif (rejected) which mixing product is the wanted and which t he unwanted image can be selected, see section 6.6. txifout txoutp txoutn avdd t1 c1 divide by 2 or 4 txlon select txip txin txqp txqn txlop divide by 2 or 4 if local oscillator -6db, 0db, +6db cmx991 tx output figure 16 cmx991 transmitter architecture the image-reject function reduces the need for filter ing following the modulator to remove spurious products, however it is likely that some filtering will still be required to meet spurious emissions limits, hence the additional filter as shown in figure 16.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 22 d/991_992/16 5.3.2 direct i/q if output tx mode as shown in figure 16, the filtered txif output from t he i/q modulator can be made available on the txifout pin. this can then be translated up to rf frequency via user-supplied external circuits or in some cases used directly for vhf operation. when this mode is selected the image-reject up-converter should be powersaved (register $14, b6 ? see section 6.5.1): this disables unused circuits and saves power. 5.4 local oscillators 5.4.1 if local oscillator the cmx991/cmx992 provides an intege r-n pll that can be used to create the if local oscillator, see figure 17. the cmx991/cmx992 provi des a vco negative resistance amplif ier, so only a tank circuit needs to be implemented externally. alternatively, this amplifier can be bypassed and an external vco can be used in the range 40 to 600 mhz. cmx991 cmx992 vco nr amplifier vcop vcon n divider (feedback) 80 - 32767 m divider (reference) 2 - 8191 phase detector vco tank & varactors fref doif vco output buffer nr control lock detect lo to i/q rx mixers (and tx if section in cmx991) enable enable figure 17 cmx991/cmx992 if local oscillator the integer-n pll has programmable m and n dividers as shown in figure 17. the phase detector provides a charge pump output which requires a suitable loop filter to convert this signal into a control voltage for a vco. the phase detector can be tur ned off (high impedance mode) and the pll section disabled if an external lo is to be used, see section 6.8 for control details. in the case of an external lo it is necessary for the vco output buffer to remain enabled (section 6.2, register $11, b1) however the vco amplifier must be disabled (register $11, b0).
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 23 d/991_992/16 the output frequency of the pll is se t by the following calculation: f out = f ref x ( n / m ) where f out = the desired output frequency in mhz f ref = the reference frequency supplied to the pll on pin fref in mhz n = divider value programmed in the n divider register (see section 6.9.1) m = divider value programmed in the m divider register (see section 6.8.1) the pll only supports vcos with a positive tuning slope, i.e. a high tuning voltage from do results in a higher oscillation frequency from the vco. the pll has a lock-detect function that can be evaluated using register $21, b6 (section 6.8.2). the vco amplifier is a negative resistance amplifier requiring an external tank circuit (see section 4.5). the amplifier has two control bits available in the general control register (section 6.2, register $11, b2 - b3). these bits can be used to optim ise performance for a particular tank circuit depending on its q value. 5.4.2 rf local oscillator the main lo for both the transmitter and the receiv er are not provided on the cmx991/cmx992 and must be supplied from an external source (see section 4.4). independent selectable internal dividers for tx and rx sections are provided to work with the external source, see figure 3 or figure 4. the input impedance is nominally 300 ? differential with a series capacitance of 6pf to each pin. ch1 s 11 1 u fs c? del prm ch2 s 11 log mag ref 0 db 5 db/ start 100.000 000 mhz stop 1 200.000 000 mhz c? prm scale 5 db/div 26 feb 2009 17:19:44 1 2 3 4 1_ 100.5 -284.67 5.5908 pf 100.000 000 mhz 2_ 35.797 -100.45 450 mhz 3_ 23.598 -64.363 820 mhz 4_ 22.861 -48.746 1 ghz 1 2 3 4 1_:-.9361 db 100.000 000 mhz 2_:-2.2931 db 450 mhz 3_:-2.9567 db 820 mhz 4_:-3.9252 db 1 ghz figure 18 typical lo input impedance
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 24 d/991_992/16 5.5 v bias the vbias pin provides a 1.6v bandgap reference-derived bias voltage (v bias ) that may be used as a reference voltage for differential amplifier stages (e .g. in the receiver output). the vbias pin can be decoupled to ground but a capacitor greater than 200nf should be used to ensure stability. 5.6 data interface the cmx991/cmx992 is controlled via a three wire c-bu s. a fourth pin (rdata) is required if register read-back is to be used. a further pin (resetn) is provided which, when ?low?, generates a reset signal (see section for 6.1 further details). the pin should be pulled to the v dd io supply with a suitable resistor if not used. the data interface can run at a lower voltage than the rest of the ic by setting the v dd io supply to the required interface voltage, in the range 1.6v to 3.6v. full details of the control register structure are given in section 6.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 25 d/991_992/16 6 c-bus interface and register description the c-bus serial interface supports the transfer of control or status information between the cmx991/cmx992s? internal registers and an external host. each c-bus transacti on consists of the host sending a single register address byte, which may then be followed by zero or more data bytes that are written into the corresponding cmx991/ cmx992 register, as illustrated in figure 19. data sent from the host to the command data (cda ta) pin is clocked into the cmx991/cmx992 on the rising edge of the serial clock (sclk) input. the c- bus interface is compatible with common c/dsp serial interfaces and may also be easily implemented with general purpose i/o pins controlled by a simple software routine. section 8.1.3.5 gives the detailed c-bus timing requirements. whether a c-bus register is of a read or write type is fixed for a given c-bus register address, thus one cannot both read and write the same c-bus register address. in order to provide ease of addressing when using this device with the cmx998, the c-bus addresses shown below are arranged so as not to overlap thos e used on the cmx998. thus, a common chip select (csn) signal can be used, as well as common cdata , rdata and sclk signals. also note that the general reset ($10) command on the cmx991/cmx992 differs from other cml devices (such as cmx998), which use $01 for this general reset function. the following c-bus register addresse s are used in the cmx991/cmx992: write only register; general reset register (address only, no data) address $10 general control register, 8-bit write only. address $11 rx control register, 8-bit write only. address $12 rx mode register, 8-bit write only. address $13 tx control register, 8-bit write only. address $14 tx mode register, 8-bit write only. address $15 tx gain register, 8-bit write only address $16 if pll m divider register, 8-bit write only address $20-$21 if pll n divider register, 8-bit write only address $22-$23 read only register; general control register, 8-bit read only. address $e1 rx control register, 8-bit read only. address $e2 rx mode register, 8-bit read only. address $e3 tx control register, 8-bit read only. address $e4 tx mode register, 8-bit read only. address $e5 tx gain register, 8-bit read only address $e6 if pll m divider register, 8-bit read only address $d0-$d1 if pll n divider register, 8-bit read only address $d2-$d3 notes: ? all registers will retain data if dvdd and vddio pi ns are held high, even if all other power supply pins are disconnected. ? if clock and data lines are shared with other devices, dv dd and v dd io must be maintained in their normal operating ranges otherwise esd protection diodes may cause a problem with loading signals connected to sclk, rdata and cdata pins, preventing correct programming of other devices. other supplies may be turned off and a ll circuits on the device may be powered down without causing this problem.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 26 d/991_992/16 figure 19 c-bus transactions
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 27 d/991_992/16 6.1 general reset command (cmx991/cmx992) 6.1.1 general reset command c-bus address $10 (no data) this command resets the device and clears all bits of all registers. the general reset command places the device into powersave mode. whenever power is applied to the dvdd pin, a built in power-on-reset circuit ensures that the device powers up into the same state as follows a gener al reset command. the resetn pin on the device will also reset the device to the same state. 6.2 general control register (cmx991/cmx992) 6.2.1 general control register: c-bus address $11 8-bit w rite-only this register controls general features of the device. all bits of this register are cleared to ?0? by a general reset command. bit: 7 6 5 4 3 2 1 0 en bias ifh chan sel rx mode vco_nr2 vco_nr1 vco_buff en vco_nr en general control register b7, b1 and b0 these bits control power up/power down of the various blocks of the ic. in all cases ?1? = power up, ?0? = power down. b7 enable bias generator. b1 enable vco buffer b0 enable vco nr amplifier. (when disabled the amplifier is bypassed to support the application of an external if lo signal.) general control register b6 if control bit, this applies to tx and rx intermediate frequencies: for if > 75mhz then set ifh = ?1?, for if < 75mhz use ifh = ?0?. general control register b5 and b4 output mode control these bits control the output mode of the rece iver. the rx mode bit determines if the output mode is i/q or if. in i/q mode both receiver output channels are enabled and the chan sel bit has no effect. in if mode only one of the receiv er output channels is enabled, as selected by the chan sel bit. note: in if mode the i or q baseband amplifier is also selected by the chan sel bit, i.e. only one of the baseband differential amplifiers can be powered up using the amp pwr bit in the rx control register.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 28 d/991_992/16 b5 b4 x 0 i/q mode: i and q channel can be enabled by bits in rx control register. 0 1 if mode: only the i channel output and i channel differential amplifier can be powered up using the rx control register. 1 1 if mode: only the q channel output and q channel differential amplifier can be powered up using the rx control register. general control register b3 and b2 vco amplifier negative resistance (nr) contro l for optimum phase noise performance. these bits control the nr (magnitude of the negativ e transconductance) of the on-chip vco nr amplifier. the nr minimum mode would thus be used with the lowest q external tank circuit and nr maximum with the highest q one. b3 b2 0 0 nr maximum 0 1 nr intermediate value 1 0 nr intermediate value 1 1 nr minimum 6.2.2 general control register c-bus address $e1 8-bit read-only this register reads the value in register $11, see section 6.2.1 for details of bit functions. 6.3 rx control register (cmx991/cmx992) 6.3.1 rx control register: c-bus address $12 8-bit w rite-only this register controls general features of the receiver such as powersave. all bits of this register are cleared to ?0? by a general reset command. bit: 7 6 5 4 3 2 1 0 mix pwr i/q pwr amp pwr sli pwr lna div2 div1 vbias rx control register b7 - b3 and b0 these bits control power up/power down of the various blocks of the ic. in all cases ?1? = power up, ?0? = power down. b7 enable receiver 1 st mixer b6 enable if amplifier/vga stage, i/q mixers, baseband filters b5 enable baseband differential amplifiers b4 enable sli amplifier b3 enable lna control signal (output pin lnaon) b0 enable v bias (bias voltage on pin 43)
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 29 d/991_992/16 rx control register b2 and b1 rf lo divider control. b2 b1 0 0 rf mixlo input divide by 2 0 1 rf mixlo input no division 1 0 rf mixlo input divide by 4 1 1 reserved ? do not use 6.3.2 rx control register c-bus address $e2 8-bit read-only this read-only register mirrors the value in register $12; see section 6.3.1 for details of bit functions. 6.4 rx mode register (cmx991/cmx992) 6.4.1 rx mode register: c-bus address $13 8-bit w rite-only this register controls operational modes of the receiver such as gain setting. all bits of this register are cleared to ?0? by a general reset command. bit: 7 6 5 4 3 2 1 0 ifin mix out i/q filter cal en vga4 vga 3 vga 2 vga 1 rx mode register b7 and b6 mixer and if amplifier signal routing. b7 select s the if input, b7 = ?0? selects ifip1 and b7 = ?1? selects ifip2. b6 selects the if output of the rx 1 st mixer, b6 = ?0? selects mixout1 and b6 = ?1? selects mixout2. b7 b6 0 0 mixer output on mixout1; if input on ifip1 and ifinn 0 1 mixer output on mixout2; if input on ifip1 and ifinn 1 0 mixer output on mixout1; if input on ifip2 and ifinn 1 1 mixer output on mixout2; if input on ifip2 and ifinn rx mode register b5 writing b5 = ?1? i/q filter bw = 1mhz; writing b5 = ?0? i/q filter bw = 100khz. rx mode register b4 enable calibration mode: disable lna and 1 st mixer when b4 = ?1?; normal operation when b4 = ?0?. for further details see section 5.2.4. rx mode register b3 - b0 vga control. for further details see section 7.3.2. b3 b2 b1 b0 1 0 0 0 vga= -48db 0 1 1 1 vga = -42db 0 1 1 0 vga = -36db 0 1 0 1 vga = -30db 0 1 0 0 vga = -24db 0 0 1 1 vga = -18db
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 30 d/991_992/16 b3 b2 b1 b0 0 0 1 0 vga = -12db 0 0 0 1 vga = -6db 0 0 0 0 vga = 0db (maximum gain) 6.4.2 rx mode register: c-bus address $e3 8-bit read-only this read-only register mirrors the value in register $13; see section 6.4.1 for details of bit functions. 6.5 tx control register (cmx991 only) 6.5.1 tx control register: c-bus address $14 8-bit w rite-only this register controls transmitter features including powersave modes. all bits of this register are cleared to ?0? by a general reset command. bit: 7 6 5 4 3 2 1 0 0 txmix pwr 0 i/q mod pwr 0 0 freq i/q out tx control register b7 - b4 these bits control power up/power down of the various blocks of the ic. in all cases ?1? = power up, ?0? = power down. b7 reserved set to ?0? b6 enable image-reject up-converter b5 reserved set to ?0? b4 enable i/q modulator, filters and its input circuits tx control register b3 and b2 reserved set to ?0?. tx control register b1 controls internal operating mode for lo circuits, set b1 = ?0? for frequency below 600mhz; set b1 = ?1? for frequencies above 600mhz. tx control register b0 with b0 = ?0? the output of the i/q modulator is connected to the image-reject up-converter; with b0 = ?1? the output of the i/q modulator is connected to the txifout output pin. 6.5.2 tx control register c-bus address $e4 8-bit read-only this read-only register mirrors the value in register $14; see section 6.5.1 for details of bit functions.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 31 d/991_992/16 6.6 tx mode register (cmx991 only) 6.6.1 tx mode register: c-bus address $15 8-bit w rite-only this register controls transmitter features. all bits of this register are cleared to ?0? by a general reset command. bit: 7 6 5 4 3 2 1 0 0 0 if_filter bw2 if_filter bw1 0 hilo txrfdiv txifdiv tx mode register b7 and b6 reserved set to ?0?. tx mode register b5 and b4 these bits select the tx if filter bandwidth: b5 b4 tx if filter bandwidth 0 0 45mhz 0 1 60mhz 1 0 90mhz 1 1 120mhz for further information see section 7.12. tx mode register b3 reserved set to ?0?. tx mode register b2 this bit controls the mixing arrangements in the image-reject up-converter as follows: b2 = ?0? f rf = f lo - f if b2 = ?1? f rf = f lo + f if tx mode register b1 controls the divider for the rf local oscilla tor: b1 = ?0? selects rf lo divided by 2 mode and b1 = ?1? selects rf lo divided by 4 mode. tx mode register b0 controls the divider for the if local oscilla tor: b0 = ?0? selects if lo divided by 4 mode and b0 = ?1? selects if lo divided by 2 mode. 6.6.2 tx mode register c-bus address $e5 8-bit read-only this read-only register mirrors the value in register $15; see section 6.6.1 for details of bit functions. 6.7 tx gain register (cmx991 only) 6.7.1 tx gain register: c-bus address $16 8-bit w rite-only this register controls transmitter gain features.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 32 d/991_992/16 all bits of this register are cleared to ?0? by a general reset command. bit: 7 6 5 4 3 2 1 0 gain2 gain1 0 0 0 0 0 0 tx gain register b7 and b6 i/q input gain control: these bits control the in ternal gain applied to input i/q signals before they are sent to the i/q modulator. b7 b6 0 0 i/q input gain = 0db 0 1 i/q input gain = -6db 1 0 i/q input gain = +6db 1 1 reserved, do not use tx gain register b5 - b0 reserved set to ?0?. 6.7.2 tx gain register c-bus address $e6 8-bit read-only this read-only register mirrors the value in register $16, see section 6.7.1 for details of bit functions. 6.8 if pll m divider (cmx991/cmx992) 6.8.1 pll m divider c-bus addresses $21 and $20 8-bit w rite-only these registers set the m divider val ue for the pll (reference divider ? see figure 17). the pll dividers are not updated until both registers ($21 and $20) have been wr itten. the order of writing these registers is not important. bits also control the enable of the pll and charge-pump blocks and these control bits are active as soon as $21 is written. $21 $20 bit: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 e ld_synth cp m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 m0 m12 - m0 phase locked loop m divider value. cp $21, b5 = ?1? enables the charge pump, $21 b5 = ?0? puts the charge pump into high impedance mode. ld_synth only write ?0? to b6 of $21 (when read, this shows the integer n pll lock status). e $21, b7 = ?1? enables the pll; b7 = ?0? disables the pll ? in this mode an external local oscillator can be supplied to the ic.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 33 d/991_992/16 6.8.2 pll m divider c-bus addresses $d1 and $d0 8 - bit read-only these registers read the respective values in registers $20 and $21 ($d0 reads back $20 and $d1 reads back $21), see section 6.8.1 for details of bit functions. note: $21 b6 indicates the lock status. if set to '1' then the pll is locked. 6.9 pll n divider (cmx991/cmx992) 6.9.1 pll n divider c-bus addresses $23 and $22 8 - bit w rite-only these registers set the n divider value for the pll (feedback divider ? see figure 17). the pll dividers are not updated until both registers ($23 and $22) have been wr itten. the order of writing these registers is not important. $23 $22 bit: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 n14 - n0 phase locked loop n divider value. $23, b7 reserved, set to ?0?. 6.9.2 pll n divider c-bus addresses $d3 and $d2 8 - bit read-only these registers read the respective values in registers $22 and $23 ($d2 reads back $22 and $d3 reads back $23), see section 6.9.1 for details of bit functions.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 34 d/991_992/16 7 application notes 7.1 general the cmx991/cmx992 chips are rf systems designed for digital wireless applications. these devices address the needs of various dat a systems, both product standards and regulatory requirements, including tetra (en 300 392-2, en 300 394-1, en 302 561) and dmr (en 300 113). apco project 25 (tia-102.caab). 7.2 using the cmx992 with the cmx998 the cmx998 device linearises an external rf pa and is an ideal complement to the cmx992. to simplify cmx992+cmx998 designs the cmx992 uses t he same physical interface architecture as the cmx998 (sdi is equivalent to cdata , sdo to rdata). the c-bus regist ers of the two devices are also compatible and allow the cmx992 and cmx998 to be connected to the same c-bus interface pins, including chip select (csn), assuming the drive capabilities of the host are adequate. 7.3 receiver gain issues 7.3.1 typical gain distribution the detailed design of a receiver for any particular application will vary. the gain of the receiver depends on the matching arrangements and impedances. a typical design partition is shown in table 13 based on the ev9910b / ev9920b evaluation pcb. thus if a ?60dbm signal is presented to the input with the matching arrangements in figure 6 (mixer) and figure 7 (if filter matching), the signal at each i and q channel output should be ~712mvp-p differential or ~ 356mvp-p on each of the differential output pins rxin, rxip, rxqp and rxqn. note that the gain of if matching and filtering must be carefully modelled: it is necessary to consider the complex matching impedances of the mixer output pins and the if input pins (see sections 7.6 and 7.7). also note that normal production tole rances will result in gain variations. input filt+ln a a ttenuato r match #1 mixer match #2 filte r match #3 if stages power -60 -60 -44 -51 -51.5 -41.5 dbm impedance 50 50 50 50 300 400 220 650 1200 ohms voltage (rms) 2.24e-04 2.24e-04 1.41e-03 6.30e-04 1.46e-03 5.32e-03 0.252 v v (p-p) 6.32e-04 6.32e-04 3.99e-03 1.78e-03 4.12e-03 1.51e-02 0.712 v output voltage pin rxip (p-p) 356 mv stage gain 0 16 -7 -0.5 10 44 db stage voltage gain 0 16 -7 7.28 11.25 44 db mixer voltage gain 18.5 dbv/v total gain 61.0 db -10.5 1.59e-03 4.49e-03 table 13 typical receiver gain partitioning notes: 1) mixer input loss based on tc1-1-13m+ at 500mhz 2) ?mixer? is cmx991 / cmx992 mixer; ?if stages ? is cmx991 / cmx992 if and i/q demodulator stages between ifin1 / ifin2 and rxin, rxip, rxqp and rxqn.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 35 d/991_992/16 7.3.2 gain adjustment the adjustment of the receiver gain is controlled by b3 ? b0 of the rx mode register ($13), see section 6.4.1. the switching of gain duri ng reception of data should be avoided as phase discontinuities will occur at transitions from ?18db to ?24db and ?24db to ?18db. t he architecture of the gain control is shown in figure 20. -18 to 0db -48 to -24db figure 20 receiver gain control 7.4 oscillator components for alternat ive intermediate frequencies. table 11 shows the tank circuit values for operating the internal if local oscillator and negative resistance amplifier at 180mhz (45mhz receive if). with reference to figure 13, typical values for other common intermediate frequencies are shown below. receiv e if frequency /mhz nr value vco frequency /mhz l1 value /nh (coilcraft type) c1 value c2 and c3 value cv1 and cv2 type mhz/v 10.7 00 42.8 220 (0805cs) 47pf 47pf smv1255- 079lf 1.25 21.4 00 85.6 100 (0805cs) 18pf 47pf jdv2s08s 2.0 70 00 280 18 (0805cs) 1.2pf 18pf jdv2s08s 6.3 90 00 360 10 (0805cs) 0.8pf 15pf jdv2s08s 5.9 110.5 01 442 5.6 (0805cs) 0.5pf 15pf jdv2s08s 5.5 note: above 400mhz reliability of operati on under all conditions cannot be guaranteed. table 14 typical if vco circuit values for a variety of if frequencies
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 36 d/991_992/16 7.5 rf mixer input matching with reference to figure 21 and table 15 below, the receiver input can be matched to alternative frequencies, with typical values shown. in a ll cases, r1, r2 = not fitted and c3, c4 = 1nf. l1 r1 l2 r2 c4 t1 mixinp mixinn input c3 cmx991/992 c1 r3 figure 21 receiver matching components component 100mhz 155mhz 850mhz 950mhz l1 220nh 150nh 0r 0r l2 2.7pf not fitted 4.7nh (0603) 6.8nh (0603) r3 0r 0r 6.8pf 3.9pf c1 not fitted 4.7pf not fitted not fitted table 15 receiver input match circuit for other operating frequencies 7.6 rf mixer if output matching in a typical implementation, the mixout pin(s) will require matching from around 500 ? U 4pf to the input of a crystal filter. the impedance of such a filter w ill often only be specified within the passband; it will be very different outside the passband. careful broad band termination of the mixout port is therefore critical in achieving the optimum intermodulation and spurious response performance from the system. the use of a shunt resistive element at mi xout is a compromise between system gain and intermodulation. values between 1,000ohms and 120ohm s can be used in practice. some shunt capacitance at mixout also helps in suppressing har monics of the rf and lo inputs that may appear at the port, so a pi network is recommended. with the matching network of figure 7, the rejection of the half if response has been found to be optimum using high side mixing.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 37 d/991_992/16 ch1 s 22 1 u fs start 10.000 000 mhz stop 150.000 000 mhz 1 2 3 4 2_: 412.42 -235.34 15.028 pf 45.000 000 mhz 1_: 539.72 -96.312 10 mhz 3_: 220.22 -251.82 100 mhz 4_: 131.29 -210.62 150 mhz figure 22 mixout1 port impedance (unmatched) frequency / mhz series impedance / parallel equivalent 10 540 ? j 96 557 // 5.1pf 45 412 - j 235 547 // 3.7pf 100 220 ? j 252 508 // 3.6pf 150 131 ? j 211 469 // 3.6pf table 16 mixout equivalent impedances 7.7 if input matching the configuration of the if input has a signific ant effect on the measured performance. this is demonstrated in table 17, where the receiver is measured wi th a 50 ohm source and three different input conditions. the typical input impedance of the ifip1 or ifip2 port is shown in figure 23, the impedance does not change much with attenuation setting ( table 18). a matched network provides the best noise figure and maximum gain, however intermodulation w ill be degraded in this condition due to the larger signal levels indicated by the extra gain. the ?strai ght in? condition means that the 50 ohm signal source was connected directly to either ifip1 or ifip2 input via a dc blocking capacitor.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 38 d/991_992/16 input condition noise figure /db gain /db 50r shunt resistor 13 43 matched network 5 61 straight in 8 49 table 17 noise figure and gain of if amp, vga, i/q mixer and baseband filters ch2 s 11 1 u fs start 10.000 000 mhz stop 150.000 000 mhz cor del prm marker 4 150 mhz 1 2 3 4 4_: 43.684 -115.87 9.1573 pf 150.000 000 mhz 1_: 582.5 -1.4823 k 10 mhz 2_: 82.813 -380.78 45 mhz 3_: 50.047 -172.98 100 mhz figure 23 ifip1 input impedance at 0db attenuation freq (mhz) 0db setting 6db setting 12db setting 18db setting 24db setting 10 4.35k //9.3pf 4.61k //9.2pf 4.80k //8.2pf 6.63k //8.3pf 4.75k //8.8pf 45 1.836k //8.9pf 1.97k //8.4pf 2.3k //7.9pf 2.21k //8.2pf 1.96k //8.8pf 100 648 //8.5pf 744 //8.0pf 776 //7.6pf 723 //7.8pf 633 //8.3pf 150 351 //8.0pf 402 //7.6pf 390 //7.3pf 365 //7.3pf 326 //7.8pf table 18 ifip1 port impedance (parallel equivalent circuit models) the gain calculated in the ?straight in? case is based on direct conversion of t he signal generator power to a voltage and calculating the gain based on the output vo ltage. the output signal is the differential signal at rxin / rxip (or rxqn and rxqp) so if the voltage is measured at a single pin the signal level must be doubled to get the appropriate differential signal leve l. also it should be noted that making a simple conversion of the power in the ?straight in? case is erroneous as the voltage calculated will be a potential difference. as the circuit is un- matched an e.m.f. would be more appropria te (i.e. twice the p.d. value).
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 39 d/991_992/16 the ?straight in? value is useful in calculating overall circuit gain, as in section 7.3.1, but it is necessary to correct for the difference between e.m.f. and p.d. i.e. reduce the gain by 6db, also the noise figure must be degraded by 6db. to exemplify this some typical measurements are shown in table 19. the theoretical correction of 6 db was actually measured at 5.4 db (which is reasonable as the 6 db figure would only be measured without any load applied to the source). the slightly positive figure for the 50 ohms is because the ifip1 pin presents an impedance that reduces the effective input impedance slightly below 50 ohms. snr for -100dbm input signal / db nf / db gain / db gain correction based on measure input voltage of 45mhz signal at ifip1 compared to the source operated into 50 ohms / db corrected gain / db corrected nf / db straight in 63 8 48.9 -5.4 43.5 13.4 50r shunt resistor 58 13 43.9 +0.2 44.1 12.8 matched 65.5 5.5 51.4 -0.6 50.8 6.1 table 19 if noise figure measurements at 45 mhz 7.8 signal level indicator (sli) the sli output is an analogue output which gives an indica tion of the signal level in the receiver if. a typical use of this signal would be to allow a hos t to control the receiver gain settings in the cmx991/cmx992. in such an application the sli pin would be connected to an analogue-to-digital converter which would sample the level at which t he host would then base the choice of gain setting on. the host would then set the appropriate gain value via c-bus (see section 6.4). when sli is enabled there is a degradation in the noise figure of the if stages. in many application circuits this degradation does not cause a significant reduction in overall receiv er sensitivity as earlier stages dominate the system noise figure. typical performance is shown in figure 24 for the ic alone (if input) and figure 25 for a typical cmx991/cmx992 receiver system, measured using the ev 9910b/ev9920b evaluation pcb.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 40 d/991_992/16 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 -100 -80 -60 -40 -20 0 20 if input level/dbm sli output/v figure 24 typical sli performance (with the signal applied to ifip1 or ifip2 and terminated with a 50ohm resistor) 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 -100 -80 -60 -40 -20 0 20 rf input level/dbm sli output/v figure 25 typical sli performance in an application circuit (ev9920b) (input 460mhz, 25khz if crystal filter: 45g15b1)
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 41 d/991_992/16 7.9 receiver spurious rejection performance the immunity of a receiver to signals away from t he wanted channel is an important factor in the overall quality of a radio receiver. receivers may suffer inte rference due to off-channel signals due to a variety of mechanisms including intermodulation, blo cking and receiver spurious responses. 7.9.1 blocking the cmx991/cmx992 blocking performance can be eval uated by injecting an unw anted signal at a 1mhz offset and observing the if output response with the unwanted signal present or not present, as shown in figure 26. the channel filtering was us ed at the if output of the cmx991 1 st mixer to ensure the spectrum analyser was capable of measuring the low levels and a lna was before the spectrum analyser to ensure the measurement was above the analyser noise floor. the results were taken with the lo path in /2 mode, lo at 820mhz. the wanted si gnal was at 455mhz @-110dbm and the unwanted was ? 18dbm at 455.9mhz. the plot in figure 26 shows the output response with (upper trace) and without (lower trace) the unwanted signal present. the noise floor rises by 3.6db when the blocker is present; note that the scale is 5db/div on plot. r f a t t 0 d b a u n i t d b m 0 . 3 d b o f f s e t r b w 2 0 0 h z v b w 2 0 0 h z s w t 1 . 5 s r e f l v l - 8 0 d b m r e f l v l - 8 0 d b m 1 k h z / c e n t e r 4 5 m h z s p a n 1 0 k h z e x t 2 s a 1 a v g 2 v i e w 2 v i e w 2 s a 1 s a - 1 2 5 - 1 2 0 - 1 1 5 - 1 1 0 - 1 0 5 - 1 0 0 - 9 5 - 9 0 - 8 5 - 1 3 0 - 8 0 1 2 1 m a r k e r 1 [ t 1 ] - 1 1 8 . 9 1 d b m 4 5 . 0 0 1 4 9 2 9 9 m h z 1 [ t 1 ] - 1 1 8 . 9 1 d b m 4 5 . 0 0 1 4 9 2 9 9 m h z 2 [ t 1 ] - 8 8 . 4 9 d b m 4 5 . 0 0 0 0 3 0 0 6 m h z 1 [ t 2 ] 3 . 5 6 d b 7 . 4 5 0 5 8 0 6 0 n h z figure 26 if output response with and without blocking signal present 7.9.2 half if response the half if response occurs at a frequency half the 1 st if frequency away from the wanted signal is a 2 nd order product. for example if re ceiving at 455mhz with a 1 st if of 45mhz and ?low side? lo at 410mhz the half if response is at 455mhz ? (45/2)mhz = 432.5mhz.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 42 d/991_992/16 the half if response of the cmx991/cmx992 is dependant on the output matching of the 1 st mixer. the arrangements described in 7.4 should be applied and matching can be optimised for a particular design. the half if performance has some variability betw een devices and care needs to be taken to ensure sufficient margin exits for device variations, a standard deviation of 1.9 may be used for such calculations. 7.10 receiver i/q filters two filtering modes are selectable using the ?i/q filt er? bit (b5 of the rx mode register, $13). the default setting of the ?i/q filter? bit is ?0? and in this case the i/q output bandwidth is limited to about 100khz. with the ?i/q filter? bit set to ?1? the i/q output has a bandwidth of approximately 1mhz. typical frequency responses for the two modes are shown in figure 27. -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 frequency / khz attenuation / db 100khz mode 1mhz mode figure 27 typical receiver i/q frequency response 7.11 modulation accuracy to check the phase error of the transmitter, a cmx 910 evaluation kit (ev9100) was used to drive the tx i/q modulator differentially with gmsk. this setup test ed 9.6kbps gmsk with a bt of 0.4, to fit in a 25khz channel. the plot in figure 28 shows the tx output acp performance as ~77dbc and table 20 shows the rms phase error as being less than 1 degree (~0.8 degrees ). the differential output level from the ev9100 is 2vp-p, therefore the 0db i/q gain setting was used.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 43 d/991_992/16 r e f l v l - 9 . 2 d b m r e f l v l - 9 . 2 d b m a 0 . 8 d b o f f s e t c e n t e r 4 6 0 m h z s p a n 6 6 k h z r b w 5 0 0 h z v b w 2 k h z s w t 1 . 3 5 s u n i t d b m 6 . 6 k h z / r f a t t 2 0 d b 1 v i e w 1 r m - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 9 - 9 . 2 1 m a r k e r 1 [ t 1 ] - 2 1 . 4 6 d b m 4 5 9 . 9 9 9 9 3 3 8 7 m h z 1 [ t 1 ] - 2 1 . 4 6 d b m 4 5 9 . 9 9 9 9 3 3 8 7 m h z c h p w r - 9 . 7 1 d b m a c p u p - 7 7 . 6 0 d b a c p l o w - 7 7 . 7 6 d b c u 1 c u 1 c l 1 c l 1 c 0 c 0 figure 28 tx output with 9.6kbps gmsk from an ev9100 (txif = 90mhz, acp ~ 77dbc)
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 44 d/991_992/16 r e f l v l - 9 . 2 d b m - 9 . 2 d b m r e f l v l - 9 . 2 d b m - 9 . 2 d b m 0 . 8 d b o f f s e t c f 4 6 0 m h z s r 9 . 6 k z s y m b o l / e r r o r s d e m o d m s k a s y m b o l t a b l e 0 0 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 4 0 1 0 1 1 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 0 1 1 1 8 0 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 0 1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 1 0 1 0 1 1 1 2 0 0 0 1 0 0 1 1 1 1 1 1 1 0 0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 6 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 2 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 0 1 0 2 4 0 0 1 0 0 0 1 e r r o r s u m m a r y e r r o r v e c t o r m a g 1 . 5 2 % r m s 4 . 1 8 % p k a t s y m 1 m a g n i t u d e e r r o r 0 . 6 4 % r m s 1 . 3 7 % p k a t s y m 6 p h a s e e r r o r 0 . 7 9 d e g r m s - 2 . 3 4 d e g p k a t s y m 1 f r e q e r r o r - 4 . 6 8 h z - 4 . 6 8 h z p k a m p l i t u d e d r o o p 0 . 1 3 d b / s y m r h o f a c t o r 0 . 9 9 8 4 i q o f f s e t 3 . 6 9 % i q i m b a l a n c e 0 . 0 6 % table 20 symbol/error table for the tx with 9.6kbps gmsk from an ev9100 7.12 post i/q modulator filter the filters following the i/q modulation process (see figure 16) are designed to reduce harmonic content of the signal. the bandwidth of the filters is select able using b4, b5 of the tx mode register ($15), see section 6.6.1. four modes are supported 45mhz, 60m hz, 90mhz and 120mhz; these frequencies do not specify the cut-off of the filters but are intended as a guide to the if frequency to be used with each filter. note however that other if frequencies may also be used. the internal filter responses are shown in figure 29. in practice the filter responses are slightly modified by the internal circuits and the res ponse at the txifout pin is shown in figure 30. it is also important to note that the ifh bit (b6, general control register $11, see section 6.2.1) has an effect on the response. ifh = ?0? is recommended for if frequencies below 75mhz and ifh = ?1? for if frequencies above 75mhz. the effect is shown in figure 31. note that 90mhz and 120mhz modes are not recommended with ifh = ?0?.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 45 d/991_992/16 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 frequency / mhz attenuation / db if=45mhz if=60mhz if=90mhz if=120mhz figure 29 transmitter path if filters -30 -25 -20 -15 -10 -5 0 25 50 75 100 125 150 transmitter if / mhz output level / dbm filter 45mhz filter 60mhz filter 90mhz filter 120mhz figure 30 transmitter if output showing filter responses with ifh bit = ?1?
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 46 d/991_992/16 -35 -30 -25 -20 -15 -10 -5 0 25 50 75 100 125 150 txif mhz o/p dbm 45mhz, ifh='0' 60mhz, ifh='0' 45mhz, ifh='1' 60mhz, ifh='1' figure 31 effect of ifh on 45mhz and 60mhz transmitter if filters
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 47 d/991_992/16 8 performance specification 8.1 electrical performance for definition of voltage and reference signal, see table 2. 8.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. esd warning : this high performance rf integrated circ uit is an esd sensitive device which has unprotected inputs and outputs. handling and assembly of this device should only be carried out at an esd protected workstation. min. max. units supply (av dd ? av ss ) or (dv dd ? dv ss ) -0.3 +4.0 v voltage on any pin to av ss or dv ss -0.3 v dd + 0.3 v voltage between av ss and dv ss -50 +50 mv voltage between av dd and dv dd -0.3 +0.3 v current into or out of dgnd, any av dd pin or dvdd -75 +75 ma current into or out of agnd (exposed metal pad) -200 +200 ma current into or out of any other pin -20 +20 ma q3 package min. max. units total allowable power dissipation at t amb = 25c ? 1750 mw ... de-rating ? 17.5 mw/c storage temperature -55 +125 c operating temperature -40 +85 c 8.1.2 operating limits correct operation of the device outsi de these limits is not implied. notes min. max. units supply (av dd ? av ss ) and (dv dd ? dv ss ) 3.0 3.6 v io supply (v dd io ? dv ss ) 1.6 3.6 v operating temperature -40 +85 c
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 48 d/991_992/16 8.1.3 operating characteristics the following conditions apply unless otherwise specified: v dd = av dd = dv dd = 3.0v to 3.6v; v ss = av ss = dv ss, t amb = -40c to +85c, sli disabled. 8.1.3.1 dc parameters dc param eters notes min. typ. max. units total current consumption powersave mode a, f ? 10 ? a v bias only c ? 2.1 2.6 ma operating currents h rx only d ? 60 80 ma synth only d ? 14 20 ma tx only (rf output) g ? 82 108 ma tx only (if output) g ? 61 76 ma current from v dd io b ? 0.3 600 a logic ?1? input level 70% ? ? v dd io logic ?0? input level ? ? 30% v dd io output logic ?1? level (l oh = 0.6 ma) 80% ? ? v dd io output logic ?0? level (l ol = -1.0 ma) ? ? +0.4 v power-up time reference voltage all blocks except reference voltage e e ? ? ? ? 0.5 10 ms s internal bandgap voltage (v bg ) 1.06 1.13 1.2 v external bias voltage (v bias ) ? derived from v bg 1.45 1.6 1.75 v notes: a. powersave mode includes the state after general reset with all analogue and digital supplies applied and also the case with v dd applied but with all analogue supplies disconnected (i.e. in this later scenario, power from v dd will not exceed the specified value whatever the state of the registers). b. assumes 30pf on each c-bus interface line and an operating serial clock frequency of 5mhz. c. the stated current drawn here is with t he bandgap reference and accompanying bias current generators enabled only (register $11, b7), all other circuitry is disabled. d. not including any current drawn from t he device pins by external circuitry: rx only ? rx circuitry plus sli (8ma), synthesiser and bias generator. synth only ? synthesiser, nr amplif ier, vco buffer and bias generator. e. as measured from the rising edge of csn. f. at t amb = 25oc, not including any current drawn fr om the cmx991/cmx992 pins by external circuitry. g. tx only ? tx circuitry plus synthesiser, vco, buffer and bias generator. if output excludes the tx image reject mixer, but includes the if output buffer. h. total current from av dd , dv dd and v dd io.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 49 d/991_992/16 8.1.3.2 ac parameters ? receiver sections rx 1 st mixer notes min. typ. max. units gain 1, 7, 7b ? 18 ? db(v/v) noise figure 7, 6b ? 11.5 ? db input third order intercept point (iip3) 450mhz 7, 7a +9.5 +11 ? dbm 950mhz 7, 7a +8 +9.5 ? dbm input frequency range 9 100 ? 1000 mhz lo frequency range 3 50 ? 1150 mhz input impedance 8 ? 300 ? ? if output frequency range 10 ? 150 mhz if output impedance ? 500 U 4pf ? ? lo leakage at input (f lo /2) 6 150mhz operation 6a ? -99 ? db 460mhz operation 6b ? -92 ? db 950mhz operation 6c ? -84 ? db 1db compression point (input) -10 -7 ? dbm half if rejection 2, 4 60 70 ? db blocking 5, 6 ? 90 ? db lo input level -10 ? 0 dbm notes: 1. measured from a low loss matched input source to a matched output load. 2. significant variation in half if reject ion can occur as a function of frequency and lo level/matching. users are recommended to optimise for a particular application. 3. lo as supplied to mixer circuit block. 4. relative level of signal at mixer if output relative to rf signal of ?30dbm; if = 45mhz and rf = 450mhz or 800mhz. 5. relative to ?107dbm (level from etsi en 300 113), based on if = 45mhz and rf = 450mhz, to give ~3db rise in mixer output noise floor. 6. including operation of selectable dividers, tested in divide by 2 mode. 6a f lo = 390mhz at ?5dbm, 45mhz if, circuit matched for 155mhz input ( table 15) 6b f lo = 1010mhz at ?5dbm, 45mhz if, circuit matched for 455mhz input ( table 4) 6c f lo = 1810mhz at ?5dbm, 45mhz if, circuit matched for 950mhz input ( table 15) 7. gain, ip3 and noise figure can be adjusted using external resistors (r1 and r2 in figure 6). 7a. measured as a system from mixer input to i/q output (pins rxin, rxip, rxqn, rxqp) and using the circuits of figure 6 and figure 7. 7b. mixer gain is the defined as 20log 10 (v in /v out ) + l match . where v in = voltage at 50 ohm input to mixer stage (?input? in figure 6); v out = voltage at mixer output (mixout1 or mixout2); l match = loss of input matching components (e.g. t1 in figure 6). 8. there is also an internal series capac itance to each mixer input of nominally 8pf. 9. the mixer can be used below 100mhz with reduced performance (see separate application note available from the cml website).
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 50 d/991_992/16 if amplifier and i/q demodulator notes min. typ. max. units gain 10, 17 ? 43 ? db(v/v) noise figure 10, 11 ? 13 ? db third order intercept point (input) 10, 17 ? -20 ? dbm input frequency range 10 ? 150 mhz lo frequency range 12 40 ? 600 mhz input impedance 15 ? 1800 ? ? output impedance ? 20 ? ? lo leakage at input ? ? -27 dbm 1db compression point 13 -30 ? ? dbm vga control range 14 ? 48 ? db vga step size 4 6 8 db vga response time e ? ? 10 s image rejection (i/q gain/phase matching) 30 40 ? db i/q output bandwidth (-3db) 1mhz mode 16 1 1.4 ? mhz 100khz mode 100 135 ? khz notes: 10. measured from an un-matched 50 ? input source to a differential i or q output voltage; test frequency = 45mhz. note that values include combined response of if amplifier, i/q demodulator and i/q filter stages. 11. at maximum vga setting (0db); see section 7.7 for further details. 12. lo supplied at four times the if frequency. 13. at maximum gain. 14. eight vga steps. 15. based on single ended input at 45mhz. 16. in 1mhz output mode an if output in the range 450khz to 465khz is supported. 17. gain reduces at higher ifs. i/q filters notes min. typ. max. units gain 20 ? n/a ? db(v/v) noise figure 20 ? n/a ? db third order intercept point (input) 20 ? n/a ? dbm output impedance 20 ? n/a ? ? output anti-alias filter stop-band 1.92 ? ? mhz stop-band attenuation 55 ? ? db data filter bandwidth (-3db) ? 100 ? khz differential output voltage swing 21 ? ? 4 vp-p notes: 20. performance included in ov erall performance of i/q demodulator. 21. this is the maximum swing to guarantee meet ing the third order distortion characteristics under the specified conditions and is not the ma ximum limiting value. for clarity, this means that the device has the capability to produce +/-1v on each of the differential outputs. the outputs are capable of drivi ng a load resistance across the differential outputs of 1k ? . this voltage output capability provi des easy interfacing to other cml devices, like the cmx981, which has a maxi mum input signal amplitude of 2.4vp-p.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 51 d/991_992/16 differential amplifiers notes min. typ. max. units gain bandwidth product 30, 33 11 14 ? mhz input offset voltage ? 1 ? mv input common mode range 32 1.0 1.6 2.5 v input bias current ? 0.4 ? a input resistance ? 160 ? k ? slew rate 30 ? 6 ? v/s differential input voltage 31 ? ? 1.2 v input referred noise at 1khz ? 15 ? nv/ hz input referred noise at 450khz ? 10 ? nv/ hz dc output range av ss +0.1 ? av dd -0.1 v notes: 30. with a load of 1k ? in parallel with 100pf referenced to a virtual earth not ground. 31. the inputs are protected with diodes. thes e diodes prevent the inadvertent application of voltages that may cause damage to the input transistors. 32. for small signal operation. it is recommended that for this application the input levels be restricted to +/-0.4v about a defined reference voltage of 1.6v (nominal); this will allow for some tolerance in components and for the precision of the setting the reference voltage. 33. gain bandwidth product typically 40mhz with 15pf load. auxiliary rx functions notes min. typ. max. units lna control enable voltage level 80% ? ? v dd io disable voltage level 0 ? 0.4 v sli output output voltage range vref. ? ? v scaling 5 10 15 mv/db operating range 35 ? 50 ? db rise time 36 ? 0.2 ? s decay time 36, 37 ? 1 ? s notes: 35. see section 7.8. 36. measured with a pulsed signal applied to ifin and terminated with 50 ? . 37. recovery from sli saturated (high input signal) takes typically an additional 500ns.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 52 d/991_992/16 8.1.3.3 ac parameters - transmitter i/q modulator notes min. typ. max. units input signal level 40 ? 2.0 ? vp-p gain control steps ? +6, 0, -6 ? db input common mode range 41 v ss +1.0 v dd /2 v dd -1.0 v input voltage range (on each input) v ss +0.5 ? v dd -0.5 v third order imd products ? ? -50 dbc imd products (greater than third order) ? ? -60 dbc carrier leakage ? -30 ? dbc image suppression ? -40 -30 dbc i or q modulation bandwidth (-3db) 42 ? ? 1 mhz notes: 40. the 2.0vp-p is a differential signal. for clarity, this means +/-0.5v on each input. 41. the common mode range is based on a 2.0vp-p differential input signal level. 42. this is the maximum modulation frequency that should be applied in the i or q channel. the bandwidth of the modulator is much hi gher than this but use of higher modulation frequencies may result in an increase in distortion products. post modulator filter notes min. typ. max. units selectable filter bandwidth ? 45, 60, 90, 120 ? mhz gain ? -2 ? db stopband (45mhz mode) >135mhz ? 30 ? db stopband (60mhz mode) >170mhz ? 30 ? db stopband (90mhz mode) >270mhz ? 30 ? db stopband (120mhz mode) >360mhz ? 30 ? db tx if output 45 frequency range 45 ? 120 mhz output signal level 46 ? -10 ? dbm wideband noise at 1mhz ? -142 ? dbc/hz output impedance ? 50 ? ? notes: 45. at pin txifout. 46. for specified i/q modulator input signal level.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 53 d/991_992/16 image-reject up-converter notes min. typ. max. units output frequency range 100 ? 1000 mhz output impedance 50 ? 2000 ? ? output level 46, 51 ? -10 ? dbm wideband noise at 1mhz ? -141 ? dbc/hz image suppression ? -36 ? dbc lo suppression (1ghz) 53 -25 -30 ? dbc lo suppression (460 mhz) ? -35 ? dbc apco p25 performance acpr (12.5khz) with c4fm 52 ? 70 ? db acpr (12.5khz) with h-cpm 52 ? 70 ? db lo input frequency range 40 ? 2000 mhz level -10 -5 0 dbm division ratios ? 2 or 4 ? notes: 50. differential output txoutp and txoutn. 51. output via 4:1 balun (see section 4.3.1) and matching to 50 ? . 52. txif of 45mhz or 90mhz; acpr meas ured as tia-102.caab-b section 3.2.8.1. 53. tested with 1910mhz lo and 45mhz if, 2vp-p differential input signal on i and q; level at 955mhz measured relative to wanted signal at 1ghz.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 54 d/991_992/16 8.1.3.4 ac parameters ? if lo integer n pll notes min. typ. max. unit phase locked loop supply current (enabled) ? 5 ? ma supply current (standby) 1 ? 1 ? a reference input frequency 5 ? 30 mhz level 90 0.5 ? ? vp-p divide ratios 2 ? 8191 if synthesiser comparison frequency ? ? 500 khz input frequency range 40 ? 600 mhz input level -10 -4 ? dbm divide ratios 80 ? 32767 charge pump current ? 2.5 ? ma 1hz normalised ssb phase noise floor 94 ? -198 ? dbc/hz vco negative resistance amplifier supply current (enabled) ? 2 ? ma supply current (standby) 1 ? 1 ? a input frequency range 93 40 ? 400 mhz phase noise at 10khz offset 91 ? -110 ? dbc/hz phase noise at 100khz offset 91 ? -125 ? dbc/hz vco output buffer supply current (enabled) ? 4 ? ma supply current (standby) 1 ? 1 ? a frequency range 40 ? 600 mhz if lo input 92 frequency range 40 ? 600 mhz level -10 -5 0 dbm division ratios ? 2 or 4 ? notes: 90. sinewave or clipped sinewave. 91. with external components forming an 180mhz vco, as shown in figure 13/ table 11 and measured after the on-chip divide by 2. 92. input to vcop and/or vcon pins, vco negative resistance amplifier disabled, see section 6.2.1). 93. operation will depend on the choice and layout of external resonant components. above 400mhz reliability of operation under all conditions cannot be guaranteed and it is recommended that an external vco be used. 94. 1hz normalised phase noise floor (pn1hz ) can be used to calculate the phase noise within the pll loop bandwidth by: measured phase noise (in 1hz) = pn1hz + 20log 10 (n) + 10log 10 (f comparison ); f comparison = f ref x ( 1 / m ), see also section 5.4.1.
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 ? 2011 cml microsystems plc 55 d/991_992/16 8.1.3.5 ac parameters ? c-bus c-bus tim ings (see figure 32 ) notes min. typ. max. units t cse csn-enable to clock-high time 100 ? ? ns t csh last clock-high to csn-high time 100 ? ? ns t loz clock-low to reply output enable time 0.0 ? ? ns t hiz csn-high to reply output 3-state time ? ? 1.0 s t csoff csn-high time between transactions 1.0 ? ? s t nxt inter-byte time 200 ? ? ns t ck clock-cycle time 200 ? ? ns t ch serial clock-high time 100 ? ? ns t cl serial clock-low time 100 ? ? ns t cds command data set-up time 75.0 ? ? ns t cdh command data hold time 25.0 ? ? ns t rds reply data set-up time 50.0 ? ? ns t rdh reply data hold time 0.0 ? ? ns maximum 30pf load on each c-bus interface line. figure 32 c-bus timing
rf quadrature transceiver / rf q uadrature receiver cmx991/cmx992 handling precautions: this pr oduct includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circu it patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of test ing every product shipped using calibrated test equipment to ensure compliance with thi s product specification. specific testing of a ll circuit parameters is not necessarily performed. 8.2 packaging notes: 1. in this device, the underside of the q3 package should be electrically connected to the analogue ground. the circuit board should be designed so that no unwant ed short circuits can occur. 2. as package dimensions may change after publication of this datasheet, it is recommended that you check for the latest packaging information from the datasheets page of the cml website: [www.cmlmicro.com]. figure 33 q3 mechanical outline: order as part no. CMX991Q3 or cmx992q3

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